**** AGGREGATE FILE 56-T57.txt 8/13/03 **** ============================================================================== **** FILE 56B-57.txt **** The Epson S1D13506 register settings below were produced by the Epson configuration program 13506CFG.exe as it was configuring a copy of the Epson program 13506BMP.exe to display 320x240x16 images on a prototype TCG057QV1AA-G00 Kyocera TFT LCD module. The S1D13506 controller IC was on an SDU1356BOC evaluation board by Epson, distributed by Kyocera as part of their SED1356 evaluation kit. CONNECTIONS This board was mounted in a PCI slot, connected to a special Kyocera interface board via a 40pin cable. The special interface board was connected to the Kyocera TFT LCD via its attached 33 pin, 0.5mm pitch white FFC cable. A connection list is below. CONFIGURATION A copy of 13506BMP.EXE, named 56B-T57.EXE, was opened, configured as described below, then saved. The TABs refer to the configuration screens in the configuration program 13506CFG.exe. REQUIRED CONFIGURATION SETTINGS (The following settings are absolutely required by the TCG057QV LCD) PANEL TAB TFT; 18 bit; Single; Color; FPline Lo; FPframe Lo; 320 width; 240 height. PREFERENCE TAB Initial display has Panel selected (otherwise NO display!) ADJUSTABLE CONFIGURATION SETTINGS (The following settings are interelated and many different combinations are possible. Anytime you change a value, 13506CFG.exe may change some other value to make your change possible. Play with it until all values are satisfactory. Here is what was used for the first trial.) PANEL TAB Non-Display Period horz 80 pixels and vert 22 lines; Timings Frame rate 60 Hz and Pixel clock 6.293 MHz; TFT/FPLINE [pixels] Start pos 44 and Pulse width 16; TFT/FPFRAME [lines] Start pos 15 and Pulse width 2. CLOCKS TAB (Nothing was set under this tab. The values shown are the result of settings made under the PANEL TAB.) CLKI Timing is Auto and 25.175 MHz is shown; LCD PCLK Source is CLKI, Divide is 4:1 and 6.294 MHz is shown; MediaPlugClk source is MCLK, Divide is 1:1 and 40.000 MHz is shown; CLKI2 is timing is Auto and 25.175 MHz is shown; BUSCLK timing is 40.000 MHz box is not checked; CRT/TV PCLK Source is CLKI2, Divide is Auto and 25.175 MHz is shown; MCLK Source is BUSCLK, Divide is 1:1 and 40.000 MHz is shown. PREFERENCE TAB Initial Display is Panel; Swivel View is 0 deg; Panel color depth is 8 bpp; CRT/TV color depth is 8 bpp. MEMORY TAB (all defaults) Refresh time 32.00 ms [per 256 cycle]; Access time is 50 ns; Memory type is EDO; WE# control is 2-CAS#; Suspend mode refresh is CAS before RAS; Installed memory is 2M. GENERAL TAB (all defaults) Decode addresses for Epson S5U13506B00B/B00C. Run 13506CFG.exe under Windows and open 13506BMP.exe or a copy of it, to get the initial values. Then modify the values as above and save. Run the copy renamed 56B-T57.exe and configured as above at the prompt on the MS-DOS emulation screen. For example c:\...>56B-T57 vw4-3224.bmp This program seems to display any .bmp image on the Kyocera TCG057QV, even 16 bpp color images. It displays the image in the upper left corner, and black fills non-image area to the right and truncates images longer than 240 lines, just as one would expect. The S1D13506 eval board has 2MB of memory, so it seems to be able to display images up to this size. For the S1D13506 IC, display memory is external. ============================================================================== CONNECTION LIST FOR TFT DEMONSTRATION INTERFACE BOARD Epson Eval Kyocera TFT Board 40pin 33pin FFC name pin pin name note FPDAT0 1 11 R5 FPDAT1 3 10 R4 FPDAT2 5 9 R3 FPDAT3 7 18 G5 FPDAT4 9 17 G4 FPDAT5 11 16 G3 FPDAT6 13 25 B5 FPDAT7 15 24 B4 FPDAT8 17 23 B3 FPDAT9 19 8 R2 FPDAT10 21 7 R1 FPDAT11 23 15 G2 FPDAT12 25 14 G1 FPDAT13 27-+-13 G0 S1D13506 provides only 16 color bits, while TCG057 +--6 R0 uses 18 color bits. So FPDAT13 is used to drive +-20 B0 all 3 least-significant bits. FPDAT14 29 22 B2 FPDAT15 31 21 B1 FPSHIFT 33 2 CK DRDY 35 27 ENAB FPLINE 37 3 HSYNC FPFRAME 39 4 VSYNC GPO 40 n/c DRDY 38 n/c VDDH 36 n/c +12V 34 n/c VCC 32-+-28 VDD +-29 VDD +-31 U/D U/D tied high for normal operation. VLCD 30 n/c n/c 28 n/c GND 2-26 Epson even numbered pins 2-26 are all GND. Any of them can be used to connect the following Kyocera pins while the others can be left n/c. 26 1 GND 24 5 GND 22 12 GND 20 19 GND 18 26 GND 16 30 R/L R/L tied to GND for normal operation. 14 32 V/Q V/Q tied to GND for normal operation. 12 33 GND ============================================================================== Below are the register contents resulting from the above configuration, obtained by the export command for generic in 13506CFG.exe, exported as a file named S1D13506.h Robert Joslyn 8/13/2003 800-826-0527 //---------------------------------------------------------------------------- // // File generated by S1D13506CFG.EXE // // Copyright (c) 2000,2001 Epson Research and Development, Inc. // All rights reserved. // //---------------------------------------------------------------------------- // Panel: (active) 320x240 60Hz TFT Single 18-bit (PCLK=CLKI/4=6.293MHz) // Memory: 50ns EDO-DRAM 2-CAS#: 32ms refresh (MCLK=BUSCLK=40.000MHz) #define S1D_DISPLAY_WIDTH 320 #define S1D_DISPLAY_HEIGHT 240 #define S1D_DISPLAY_BPP 8 #define S1D_DISPLAY_SCANLINE_BYTES 320 #define S1D_PHYSICAL_VMEM_ADDR 0x00000000L #define S1D_PHYSICAL_VMEM_SIZE 0x200000L #define S1D_PHYSICAL_REG_ADDR 0x00000000L #define S1D_PHYSICAL_REG_SIZE 0x200 #define S1D_DISPLAY_PCLK 6293 #define S1D_PALETTE_SIZE 256 #define S1D_REGDELAYOFF 0xFFFE #define S1D_REGDELAYON 0xFFFF #define S1D_WRITE_PALETTE(p,i,r,g,b) \ { \ ((volatile S1D_VALUE*)(p))[0x1E2/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(r); \ ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(g); \ ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(b); \ } #define S1D_READ_PALETTE(p,i,r,g,b) \ { \ ((volatile S1D_VALUE*)(p))[0x1E2/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ r = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ g = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ b = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ } typedef unsigned short S1D_INDEX; typedef unsigned char S1D_VALUE; typedef struct { S1D_INDEX Index; S1D_VALUE Value; } S1D_REGS; static S1D_REGS aS1DRegs[] = { {0x0001,0x00}, // Miscellaneous Register {0x01FC,0x00}, // Display Mode Register {0x0004,0x00}, // General IO Pins Configuration Register {0x0008,0x00}, // General IO Pins Control Register {0x0010,0x01}, // Memory Clock Configuration Register {0x0014,0x30}, // LCD Pixel Clock Configuration Register {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register {0x001C,0x03}, // MediaPlug Clock Configuration Register {0x001E,0x01}, // CPU To Memory Wait State Select Register {0x0020,0x00}, // Memory Configuration Register {0x0021,0x06}, // DRAM Refresh Rate Register {0x002A,0x01}, // DRAM Timings Control Register 0 {0x002B,0x01}, // DRAM Timings Control Register 1 {0x0030,0x25}, // Panel Type Register {0x0031,0x00}, // MOD Rate Register {0x0032,0x27}, // LCD Horizontal Display Width Register {0x0034,0x09}, // LCD Horizontal Non-Display Period Register {0x0035,0x05}, // TFT FPLINE Start Position Register {0x0036,0x01}, // TFT FPLINE Pulse Width Register {0x0038,0xEF}, // LCD Vertical Display Height Register 0 {0x0039,0x00}, // LCD Vertical Display Height Register 1 {0x003A,0x15}, // LCD Vertical Non-Display Period Register {0x003B,0x0E}, // TFT FPFRAME Start Position Register {0x003C,0x01}, // TFT FPFRAME Pulse Width Register {0x0040,0x03}, // LCD Display Mode Register {0x0041,0x00}, // LCD Miscellaneous Register {0x0042,0x00}, // LCD Display Start Address Register 0 {0x0043,0x00}, // LCD Display Start Address Register 1 {0x0044,0x00}, // LCD Display Start Address Register 2 {0x0046,0xA0}, // LCD Memory Address Offset Register 0 {0x0047,0x00}, // LCD Memory Address Offset Register 1 {0x0048,0x00}, // LCD Pixel Panning Register {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register {0x0053,0x01}, // CRT/TV HRTC Start Position Register {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0 {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1 {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register {0x0059,0x09}, // CRT/TV VRTC Start Position Register {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register {0x005B,0x10}, // TV Output Control Register {0x0060,0x03}, // CRT/TV Display Mode Register {0x0062,0x00}, // CRT/TV Display Start Address Register 0 {0x0063,0x00}, // CRT/TV Display Start Address Register 1 {0x0064,0x00}, // CRT/TV Display Start Address Register 2 {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0 {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1 {0x0068,0x00}, // CRT/TV Pixel Panning Register {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register {0x0070,0x00}, // LCD Ink/Cursor Control Register {0x0071,0x01}, // LCD Ink/Cursor Start Address Register {0x0072,0x00}, // LCD Cursor X Position Register 0 {0x0073,0x00}, // LCD Cursor X Position Register 1 {0x0074,0x00}, // LCD Cursor Y Position Register 0 {0x0075,0x00}, // LCD Cursor Y Position Register 1 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register {0x007A,0x00}, // LCD Ink/Cursor Blue Color 1 Register {0x007B,0x00}, // LCD Ink/Cursor Green Color 1 Register {0x007C,0x00}, // LCD Ink/Cursor Red Color 1 Register {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register {0x0082,0x00}, // CRT/TV Cursor X Position Register 0 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register {0x008A,0x00}, // CRT/TV Ink/Cursor Blue Color 1 Register {0x008B,0x00}, // CRT/TV Ink/Cursor Green Color 1 Register {0x008C,0x00}, // CRT/TV Ink/Cursor Red Color 1 Register {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register {0x0100,0x00}, // BitBlt Control Register 0 {0x0101,0x00}, // BitBlt Control Register 1 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register {0x0103,0x00}, // BitBlt Operation Register {0x0104,0x00}, // BitBlt Source Start Address Register 0 {0x0105,0x00}, // BitBlt Source Start Address Register 1 {0x0106,0x00}, // BitBlt Source Start Address Register 2 {0x0108,0x00}, // BitBlt Destination Start Address Register 0 {0x0109,0x00}, // BitBlt Destination Start Address Register 1 {0x010A,0x00}, // BitBlt Destination Start Address Register 2 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1 {0x0110,0x00}, // BitBlt Width Register 0 {0x0111,0x00}, // BitBlt Width Register 1 {0x0112,0x00}, // BitBlt Height Register 0 {0x0113,0x00}, // BitBlt Height Register 1 {0x0114,0x00}, // BitBlt Background Color Register 0 {0x0115,0x00}, // BitBlt Background Color Register 1 {0x0118,0x00}, // BitBlt Foreground Color Register 0 {0x0119,0x00}, // BitBlt Foreground Color Register 1 {0x01E0,0x00}, // Look-Up Table Mode Register {0x01E2,0x00}, // Look-Up Table Address Register {0x01E4,0x00}, // Look-Up Table Data Register {0x01F0,0x00}, // Power Save Configuration Register {0x01F1,0x00}, // Power Save Status Register {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register {0x01FC,0x01}, // Display Mode Register }; //----------------------------------------------------------------------------