**** AGGREGATE FILE 56-G57.txt 10/17/03 **** ==================================================== **** FILE 56B-G57.txt **** This document shows how to use the Epson program 13506CFG.exe to determine the Epson S1D13506 controller IC register settings for the Kyocera KCG057QV.. LCD and how to put the register settings into an executable file and test them on the LCD. The S1D13506 was on an SDU1356BOC evaluation board by Epson. BEGIN with a MS-Windows computer with an open PCI slot. Copy the "drivers" from the S1D13xxx folder into the root directory. Copy the Epson S1D13506 software utilities into a working folder. Copy 13506BMP.EXE into the same folder to create a duplicate. Rename the duplicate 56B-G57.EXE Power down for connections. CONNECTIONS This board was mounted in a PCI slot and connected to a Kyocera KK-5 No.1 interface board via a 40pin cable. The KK-5 was connected to a Kyocera KK-7 connector board LCD via a red Molex cable, which was inserted in the KK-5 connector with white paper label saying "CN6" and into the KK-7 connector named CN5 by screen printing on the board. The KCG LCD was connected to the KK-7 board by a white 20-pin FFC. RUN 13506CFG.EXE under windows File->Open->56B-G57.EXE GENERAL TAB Select Epson S5u13506BooB/Booc PREFERENCE TAB Initial Display: select Panel Panel Swivel View: select 0 degrees Pixel Color Depth: select 8 bpp CRT/TV Color Depth: select 8 bpp (does not matter) MEMORY TAB: accept all defaults CRT/TV TAB: accept all defaults PANEL TAB: (The following settings are absolutely required by the Kyocera KCG057QV LCD panel) Panel Settings: select STN, select 8 bit Dual Panel: select Single Panel Color: select Color, select Format 2 Polarity: select FPLINE Hi and FPFRAME Hi Panel Dimensions: Width select 320, Height select 240 (The following settings are interelated and many different combinations are possible.) Non-display Period: Horiz. select 64 pixels, Vert. select 1 line Timings: Pixel Clock select 13.333 mHz which sets frame rate to 144 Hz. (Section 5 of the Kyocera spec gives the required range of the shift clock frequency. The maximum shift clock frequency is important. The maximum frame rate frequency does not matter. Shift-clock-Freq = (3/8) x Pixel-Clock-Freq 3 comes from 3 LCD subpixels per pixel. 8 comes from 8 data lines per clock pulse. CLOCKS TAB (Do not set anything under this tab because the values are set by your selection of pixel clock frequency and non-display periods. If you do set frequencies in the CLOCKS TAB, then please note the changes which are automatically made under PANEL TAB.) REGISTERS TAB File->Export->Generic change name from S1D13506.H to 57B-G57.H Click Export (eventually give this .h file to your software engineers) File->Save (patches the above register settings into the executable code in 56B-G57.EXE) TEST THE SETTINGS Start the MS-DOS emulation window (not RUN ..) >CD {your working folder} >56B-G57 {observe the Help info} >56B-G57 PE8-3224.BMP {or other sample bitmap} Of course you will need a TDK inverter to power the LCD backlight and a cable and a 12V power supply to power the inverter. This program seems to display any .bmp image on the Kyocera KCG057QV. It displays the image in the upper left corner and black fills any non-image area to the right and truncates images longer than 240 lines, just as you would expect. The S1D13506 has 2MB of memory, so it seems to be able to display images up to this size. But, unlike the 1374, it will not correctly display images with 1 bpp color. The default color depth of 8 bpp under the PREFERENCE TAB seems to an initializing value, used by the program before it opens the .bmp file. Below are the register values as formatted above in 56B-G57.H Robert Joslyn 10/17/03 800-826-0527 or 360-750-6121 //---------------------------------------------------------------------------- // // File generated by S1D13506CFG.EXE // // Copyright (c) 2000,2001 Epson Research and Development, Inc. // All rights reserved. // //---------------------------------------------------------------------------- // Panel: (active) 320x240 144Hz STN Single 8-bit (PCLK=CLKI/3=13.333MHz) (Color Format 2) // Memory: 50ns EDO-DRAM 2-CAS#: 32ms refresh (MCLK=BUSCLK=40.000MHz) #define S1D_DISPLAY_WIDTH 320 #define S1D_DISPLAY_HEIGHT 240 #define S1D_DISPLAY_BPP 8 #define S1D_DISPLAY_SCANLINE_BYTES 320 #define S1D_PHYSICAL_VMEM_ADDR 0x00000000L #define S1D_PHYSICAL_VMEM_SIZE 0x200000L #define S1D_PHYSICAL_REG_ADDR 0x00000000L #define S1D_PHYSICAL_REG_SIZE 0x200 #define S1D_DISPLAY_PCLK 13333 #define S1D_PALETTE_SIZE 256 #define S1D_REGDELAYOFF 0xFFFE #define S1D_REGDELAYON 0xFFFF #define S1D_WRITE_PALETTE(p,i,r,g,b) \ { \ ((volatile S1D_VALUE*)(p))[0x1E2/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(r); \ ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(g); \ ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(b); \ } #define S1D_READ_PALETTE(p,i,r,g,b) \ { \ ((volatile S1D_VALUE*)(p))[0x1E2/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ r = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ g = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ b = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ } typedef unsigned short S1D_INDEX; typedef unsigned char S1D_VALUE; typedef struct { S1D_INDEX Index; S1D_VALUE Value; } S1D_REGS; static S1D_REGS aS1DRegs[] = { {0x0001,0x00}, // Miscellaneous Register {0x01FC,0x00}, // Display Mode Register {0x0004,0x00}, // General IO Pins Configuration Register {0x0008,0x00}, // General IO Pins Control Register {0x0010,0x01}, // Memory Clock Configuration Register {0x0014,0x20}, // LCD Pixel Clock Configuration Register {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register {0x001C,0x03}, // MediaPlug Clock Configuration Register {0x001E,0x01}, // CPU To Memory Wait State Select Register {0x0020,0x00}, // Memory Configuration Register {0x0021,0x06}, // DRAM Refresh Rate Register {0x002A,0x01}, // DRAM Timings Control Register 0 {0x002B,0x01}, // DRAM Timings Control Register 1 {0x0030,0x1C}, // Panel Type Register {0x0031,0x00}, // MOD Rate Register {0x0032,0x27}, // LCD Horizontal Display Width Register {0x0034,0x07}, // LCD Horizontal Non-Display Period Register {0x0035,0x01}, // TFT FPLINE Start Position Register {0x0036,0x0B}, // TFT FPLINE Pulse Width Register {0x0038,0xEF}, // LCD Vertical Display Height Register 0 {0x0039,0x00}, // LCD Vertical Display Height Register 1 {0x003A,0x00}, // LCD Vertical Non-Display Period Register {0x003B,0x0B}, // TFT FPFRAME Start Position Register {0x003C,0x01}, // TFT FPFRAME Pulse Width Register {0x0040,0x03}, // LCD Display Mode Register {0x0041,0x00}, // LCD Miscellaneous Register {0x0042,0x00}, // LCD Display Start Address Register 0 {0x0043,0x00}, // LCD Display Start Address Register 1 {0x0044,0x00}, // LCD Display Start Address Register 2 {0x0046,0xA0}, // LCD Memory Address Offset Register 0 {0x0047,0x00}, // LCD Memory Address Offset Register 1 {0x0048,0x00}, // LCD Pixel Panning Register {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register {0x0053,0x01}, // CRT/TV HRTC Start Position Register {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0 {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1 {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register {0x0059,0x09}, // CRT/TV VRTC Start Position Register {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register {0x005B,0x10}, // TV Output Control Register {0x0060,0x03}, // CRT/TV Display Mode Register {0x0062,0x00}, // CRT/TV Display Start Address Register 0 {0x0063,0x00}, // CRT/TV Display Start Address Register 1 {0x0064,0x00}, // CRT/TV Display Start Address Register 2 {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0 {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1 {0x0068,0x00}, // CRT/TV Pixel Panning Register {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register {0x0070,0x00}, // LCD Ink/Cursor Control Register {0x0071,0x01}, // LCD Ink/Cursor Start Address Register {0x0072,0x00}, // LCD Cursor X Position Register 0 {0x0073,0x00}, // LCD Cursor X Position Register 1 {0x0074,0x00}, // LCD Cursor Y Position Register 0 {0x0075,0x00}, // LCD Cursor Y Position Register 1 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register {0x007A,0x00}, // LCD Ink/Cursor Blue Color 1 Register {0x007B,0x00}, // LCD Ink/Cursor Green Color 1 Register {0x007C,0x00}, // LCD Ink/Cursor Red Color 1 Register {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register {0x0082,0x00}, // CRT/TV Cursor X Position Register 0 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register {0x008A,0x00}, // CRT/TV Ink/Cursor Blue Color 1 Register {0x008B,0x00}, // CRT/TV Ink/Cursor Green Color 1 Register {0x008C,0x00}, // CRT/TV Ink/Cursor Red Color 1 Register {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register {0x0100,0x00}, // BitBlt Control Register 0 {0x0101,0x00}, // BitBlt Control Register 1 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register {0x0103,0x00}, // BitBlt Operation Register {0x0104,0x00}, // BitBlt Source Start Address Register 0 {0x0105,0x00}, // BitBlt Source Start Address Register 1 {0x0106,0x00}, // BitBlt Source Start Address Register 2 {0x0108,0x00}, // BitBlt Destination Start Address Register 0 {0x0109,0x00}, // BitBlt Destination Start Address Register 1 {0x010A,0x00}, // BitBlt Destination Start Address Register 2 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1 {0x0110,0x00}, // BitBlt Width Register 0 {0x0111,0x00}, // BitBlt Width Register 1 {0x0112,0x00}, // BitBlt Height Register 0 {0x0113,0x00}, // BitBlt Height Register 1 {0x0114,0x00}, // BitBlt Background Color Register 0 {0x0115,0x00}, // BitBlt Background Color Register 1 {0x0118,0x00}, // BitBlt Foreground Color Register 0 {0x0119,0x00}, // BitBlt Foreground Color Register 1 {0x01E0,0x00}, // Look-Up Table Mode Register {0x01E2,0x00}, // Look-Up Table Address Register {0x01E4,0x00}, // Look-Up Table Data Register {0x01F0,0x00}, // Power Save Configuration Register {0x01F1,0x00}, // Power Save Status Register {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register {0x01FC,0x01}, // Display Mode Register };