**** AGGREGATE FILE 74-65.txt  5/17/01 ****

========================================================

    **** FILE 74B-65.txt ****

This SED1374 register listing was made while displaying
a 640x240x1 black and white image on a Kyocera
KCB065HV... LCD panel.  The configuration attributes
chosen in 1374CFG.EXE were:

  color,single,STN,8 bit,format 2,
  640x240, Lookup Table 1bpp, 
  memory location 0xD0000,
  frame rate 75 fps, input clock 12500 kHz.

All other boxes were unchecked or unchangeable
defaults.  1374bmp.exe configured as above
is saved under name 74B-65.exe
The 1374 has enough memory for 4 colors (2bpp), but
my PaintShopPro software could not make a 2bpp .bmp
file.   --R. Joslyn 3/23/018


1374PLAY - test utility - version 1.00 (HAL 1.00)

=xa
=
[00] > 18  00011000b  024t	[01] > 23  00100011b  035t
[02] > 00  00000000b  000t	[03] > 03  00000011b  003t
[04] > 4F  01001111b  079t	[05] > EF  11101111b  239t
[06] > 00  00000000b  000t	[07] > 00  00000000b  000t
[08] > 02  00000010b  002t	[09] > 00  00000000b  000t
[0A] > 02  00000010b  002t	[0B] > 00  00000000b  000t
[0C] > 00  00000000b  000t	[0D] > 00  00000000b  000t
[0E] > 00  00000000b  000t	[0F] > 00  00000000b  000t
[10] > 00  00000000b  000t	[11] > 00  00000000b  000t
[12] > 00  00000000b  000t	[13] > FF  11111111b  255t
[14] > 03  00000011b  003t	[15] > 02  00000010b  002t
[16] > 00  00000000b  000t	[17] > 00  00000000b  000t
[18] > 00  00000000b  000t	[19] > 00  00000000b  000t
[1A] > 00  00000000b  000t	[1B] > 00  00000000b  000t
[1C] > 00  00000000b  000t
=q
=

==========================================================

    **** FILE 74-65pin.txt ****

Here is the connection table between the Epson SED 1374 
controller IC (not the eval board) and the Kyocera 6.5 
inch 640x240 LCD modules (K_B065HV...).
I made this table from studying specifications.
I am fairly certain that is is correct but I
have not confirmed it by building a device. 


SED	SED		KC	KC
PIN	PIN		PIN	PIN
NAME	NO.		NO.	NAME

FPDAT0	37	=====	9	D0
FPDAT1	36	=====	10	D1
FPDAT2	35	=====	11	D2
FPDAT3	34	=====	12	D3
FPDAT4	33	=====	13	D4
FPDAT5	32	=====	14	D5
FPDAT6	31	=====	15	D6
FPDAT7	30	=====	16	D7
FPSHIFT	28	=====	3	CP
FPLINE	38	=====	2	LOAD
FPFRAM	39	=====	1	FRM

NOT DIRECTLY FROM SED
 enable		=====	4	DISP
 1.3~2.6 VDC 
   (adjustable)	=====	7	VCONT
 3.3 VDC logic	=====	5	VDD
 GND		=====	17,18	VSS
 GND		=====	6,8	VSS


The K*B065HV... family of Kyocera HVGA
6.5" LCD modules contains additional 
circuits internally to provide periodic 
voltage inversion ("randomizing") and
bias voltages.  Therefore the DF and
V0~V5 signals are not inputs to these
LCDs.  Furthermore, these LCDs contain
DC-DC converters, so that no adjustable
driving voltages are required, although
a low voltage contrast adjustment is
still required. 

Robert Joslyn    5/17/01
Kyocera Industrial Ceramics
360-992-1859 

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