**** AGGREGATE FILE 75-47.txt  8/25/03 ****
    ****    Robert Joslyn, 800-826-0527    ****
    ****    Kyocera Industrial Ceramics    ****
    ****    email bob.joslyn@kyocera.com   ****

**********************************************************************

 
These S1D13705 register contents were taken while displaying a 
320x240x8 image on a KCG047QV... Kyocera LCD module.  The S1D13705  
was mounted on an SDU1375BOC rev 1.0 evaluation board by Epson.
The same values would be used for a KCG057QV... LCD.

CONNECTIONS
  This board was mounted in an ISA slot and connected to a Kyocera 
  KK5 No.1 interface board via 40pin cable.  The KK5 was connected to 
  the Kyocera KK-7 via the red cable, which was inserted in the KK-5 
  connector having a white paper label saying "CN6".  The KK-7 board 
  was connected to the KCG-series LCD via a 20 pin FFC having all 
  contacts on the same surface of the flat cable.


REGISTER CONFIGURATION  
  A copy of 13705BMP.exe was made, renamed 75B-47.exe
  and configured with 13705CFG.exe as follows:

 PANEL TAB
 (The following PANEL TAB settings are absolutely required
 by the Kyocera KCG047QV LCD modules)

    STN; Format 2; 8-bit; Color; Single; FPLINE=High;
    FPFRAME=High; Panel Width=320; Panel Height=240.
 

 (The following settings are acceptable for this LCD)

    Non-display periods H=32 pixels, V=0 lines 
    Frame rate (fps)=71, Pixel clock (MHz)=6.000.
    Therefore Kyocera CP freq = 3/8 PixelClock = 2.25 MHz.

 CLOCKS TAB (Defaults from PANEL TAB choices)
    CLKI=6.000MHz, Actual=6.000MHz, CLKI/2 unchecked.
    PCLK Source CLKI, Divide=1:1, Timing=6.000MHZ.
    MCLK Source CLKI, Divide=1:1, Timing=6.000MHZ.

 PREFERENCES TAB
    Color depth=8bpp, SwivelView Enable unchecked.

    
 GENERAL TAB
    Selected Epson S5U13705B/B00C.  
    Grayed-out Display buffer address = 00F00000.

    The PC had a VGA adapter, so the SDU1375 eval board had to be 
    jumpered to use F00000 of ISA bus memory, per section 6.2.1 of 
    the Epson User Manual.  The Gateway P5-120 PC had to have this 
    BIOS setting change:
    Under ADVANCED TAB,  in the Advanced Chipset Configuration Menu, 
    "ISA LFB Size" had to be set to "1MB" (instead of to default 
    "Disabled") to free up bus memory address 00F00000.

 PANEL POWER TAB
    Used the default settings which were
      Hardware Power Save Enable box checked.
      Time delay between LCD control signals active
        and LCD bias power-on: 0 ms.
      Time delay between LCD bias power-off and 
        LCD control signals inactive: 500 ms.
 
SAVING CONFIGURATION VALUES
 Run 13705CFG.exe under windows.  To get the default values, open 
 13705BMP.exe or a renamed copy of it, for example 75B-47.exe, then 
 modify as above and click File->Save.

OPERATING THE LCD
 Start the MS-DOS emulation window under "Accessories".
 Run the program renamed 74B-57.exe and configured as above at the 
 prompt on the MS-DOS emulation screen.  For example:

    c:\...>75B-47 BL4-3224.bmp

 If the bitmap is too big for the s1D13705 chip's 80kB display memory,  
 then an error message is displayed.  There is enough memory for .bmp 
 files with  320 pixels x 240 lines x 8 bit color.

REGISTER VALUES
 Below are this configuration's register values from 
     File->Export->C Header File for S1D13705 Generic Drivers,
 produced in a text file named S1D13705.h
 
**********************************************************************


//==================================================================
//
//  Generic Header information generated by 13705CFG.EXE (Build 9)
//
//  Copyright (c) 2000,2001 Epson Research and Development, Inc.
//  All rights reserved.
//
//  Panel: 320x240x8bpp 71Hz Color 8-Bit STN, Format 2 (PCLK=6.000MHz)
//
//  This file defines the configuration environment and registers,
//  which can be used by any software, such as display drivers.
//
//  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
//               sure you transfer this file using ASCII, not BINARY
//               mode.
//
//==================================================================

#define S1D_DISPLAY_WIDTH               320
#define S1D_DISPLAY_HEIGHT              240
#define S1D_DISPLAY_BPP                 8
#define S1D_DISPLAY_SCANLINE_BYTES      320
#define S1D_DISPLAY_FRAME_RATE          71
#define S1D_DISPLAY_PCLK                6000000L
#define S1D_PHYSICAL_REG_ADDR           0x00F1FFE0L
#define S1D_PHYSICAL_VMEM_ADDR          0x00F00000L
#define S1D_PHYSICAL_REG_SIZE           31L
#define S1D_PHYSICAL_VMEM_SIZE          81920L
#define S1D_PALETTE_SIZE                256
#define S1D_FRAME_RATE                  71
#define S1D_POWER_DELAY_OFF             500
#define S1D_POWER_DELAY_ON              0
#define S1D_REGDELAYOFF                 0xFE
#define S1D_REGDELAYON                  0xFF

#define S1D_WRITE_PALETTE(p,i,r,g,b)  \
  {  \
  ((volatile S1D_VALUE*)(p))[0x15/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);
  ((volatile S1D_VALUE*)(p))[0x17/sizeof(S1D_VALUE)] = (S1D_VALUE)(r);
  ((volatile S1D_VALUE*)(p))[0x17/sizeof(S1D_VALUE)] = (S1D_VALUE)(g);
  ((volatile S1D_VALUE*)(p))[0x17/sizeof(S1D_VALUE)] = (S1D_VALUE)(b);
  }

#define S1D_READ_PALETTE(p,i,r,g,b)   \
  {  \
  ((volatile S1D_VALUE*)(p))[0x15/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);
  r = ((volatile S1D_VALUE*)(p))[0x17/sizeof(S1D_VALUE)]; \
  g = ((volatile S1D_VALUE*)(p))[0x17/sizeof(S1D_VALUE)]; \
  b = ((volatile S1D_VALUE*)(p))[0x17/sizeof(S1D_VALUE)]; \
  }

typedef unsigned char S1D_INDEX;
typedef unsigned char S1D_VALUE;
typedef struct
{
    S1D_INDEX Index;
    S1D_VALUE Value;
} S1D_REGS;

static S1D_REGS aS1DRegs[] =
{
    { 0x00, 0x24 },  // Revision Code Register
    { 0x01, 0x3B },  // Mode Register 0 Register
    { 0x02, 0xE0 },  // Mode Register 1 Register
    { 0x03, 0x07 },  // Mode Register 2 Register
    { 0x04, 0x27 },  // Horizontal Panel Size Register
    { 0x05, 0xEF },  // Vertical Panel Size Register (LSB)
    { 0x06, 0x00 },  // Vertical Panel Size Register (MSB)
    { 0x07, 0x05 },  // FPLINE Start Position Register
    { 0x08, 0x00 },  // Horizontal Non-Display Period Register
    { 0x09, 0x04 },  // FPFRAME Start Position Register
    { 0x0A, 0x00 },  // Vertical Non-Display Period Register
    { 0x0B, 0x00 },  // MOD Rate Register
    { 0x0C, 0x00 },  // Screen 1 Start Address Register (LSB)
    { 0x0D, 0x00 },  // Screen 1 Start Address Register (MSB)
    { 0x0E, 0x00 },  // Screen 2 Start Address Register (LSB)
    { 0x0F, 0x00 },  // Screen 2 Start Address Register (MSB)
    { 0x10, 0x00 },  // Screen Start Address Overflow Register
    { 0x11, 0x00 },  // Memory Address Offset Register
    { 0x12, 0xFF },  // Screen 1 Vertical Size Register (LSB)
    { 0x13, 0x03 },  // Screen 1 Vertical Size Register (MSB)
    { 0x14, 0x00 },  // Not Used
    { 0x15, 0x00 },  // Look-Up Table Address Register
    { 0x16, 0x00 },  // Not Used
    { 0x17, 0x00 },  // Look-Up Table Data Register
    { 0x18, 0x00 },  // GPIO Configuration Control Register
    { 0x19, 0x02 },  // GPIO Status/Control Register
    { 0x1A, 0x00 },  // Scratch Pad Register
    { 0x1B, 0x00 },  // SwivelView Mode Register
    { 0x1C, 0x00 },  // Line Byte Count Register
    { 0x1D, 0x00 },  // Not Used
    { 0x1E, 0x00 },  // Not Used
    { 0x1F, 0x00 },  // Not Used
};

**********************************************************************

Below are the live register settings captured by 13705PLAY.exe
into a text file while displaying a 320x240x8bit image.  

In the MS-DOS window press the enter key to exit 75B-47.  The image 
will continue to display from the board.

C:\...>13705PLAY >anyname.txt
xa
q
C:\...>

**********************************************************************

13705PLAY - test utility - version 1.01 (HAL 1.05)
Copyright (c) 1998, 2001 Epson Research and Development, Inc.
All Rights Reserved.

=
=
[00] > 24  00100100b  036t	[01] > 3B  00111011b  059t
[02] > E0  11100000b  224t	[03] > 07  00000111b  007t
[04] > 27  00100111b  039t	[05] > EF  11101111b  239t
[06] > 00  00000000b  000t	[07] > 05  00000101b  005t
[08] > 00  00000000b  000t	[09] > 04  00000100b  004t
[0A] > 00  00000000b  000t	[0B] > 00  00000000b  000t
[0C] > 00  00000000b  000t	[0D] > 00  00000000b  000t
[0E] > 00  00000000b  000t	[0F] > 00  00000000b  000t
[10] > 00  00000000b  000t	[11] > 00  00000000b  000t
[12] > FF  11111111b  255t	[13] > 03  00000011b  003t
[14] > 00  00000000b  000t	[15] > 00  00000000b  000t
[16] > 00  00000000b  000t	[17] > 10  00010000b  016t
[18] > 00  00000000b  000t	[19] > 00  00000000b  000t
[1A] > 00  00000000b  000t	[1B] > 00  00000000b  000t
[1C] > 00  00000000b  000t
=
=

**********************************************************************


Here is the connection table between Epson S1D13705 controller IC 
(not the eval board) and Kyocera QVGA LCD modules, made from
studying the specifications.


S1D	S1D		KC	KC
PIN	PIN		PIN	PIN
NAME	NO.		NO.	NAME

FPDAT0	37	=====	15	D0
FPDAT1	36	=====	14	D1
FPDAT2	35	=====	13	D2
FPDAT3	34	=====	12	D3
FPDAT4	33	=====	11	D4
FPDAT5	32	=====	10	D5
FPDAT6	31	=====	9	D6
FPDAT7	30	=====	8	D7
FPSHIFT	28	=====	3	CP
FPLINE	38	=====	2	LOAD
FPFRAM	39	=====	1	FRM

NOT DIRECTLY FROM SED
 enable		=====	4	DISP
 0.8 to 2.8 VDC 
   (adjustable)	=====	7	VCONT
 3.3 VDC logic	=====	16	VDD
                +====   17      VDD
 GND		=====	18	VSS
 		+====	19	VSS
 		+====	20	VSS


The KCG family of Kyocera STN QVGA LCD modules contains additional 
circuits internally to provide periodic voltage inversion 
("randomizing"), DC-DC conversion, and bias voltages.  Therefore 
the DF and V0~V5 signals are not inputs to these LCDs.

**********************************************************************