**** AGGREGATE FILE 76-65.txt 5/17/01 **** ====================================================== **** FILE 76B-65.txt **** These SED1376 register contents were taken while displaying a 640x240x4 image on a KCB065HV1AB Kyocera LCD module. The SED1376 was on an SDU1376BOC evaluation board by Epson. This board was mounted in a PCI slot, connected to a Kyocera KK5 No.1 interface board via 40pin cable. The KK5 was connected to the KCB065HV1 via an 18pin FFC. The FFC was inserted into a connector on the KK5 identified as CN3 by a white paper label. It is the only 18 pin connector on the KK-5 board. The two ends of the FFC had the exposed metal contact surfaces on the same side of the FF. The FFC inserts metal-side-up into the connector on the KK-5 and metal-side-down into the connector on the back of the LCD, so that LCD, KK5 and FFC all lie flat when the LCD is flipped over with display side up. I made a copy of 1376BMP.EXE, named 76B-65.exe and configured it as follows: PANEL TAB color, format2, STN, 8bit, FPline Hi, FPframe Hi, 640 wide, 240 high, Display Total H[pxl] 656 and V[line] 251, Display Start H[pxl] 22 and V[line] 0, Frame Rate 75Hz, PClk 12500kHz, FPLINE[pixels] Start Pos.=0 and Pulse Width=8, FPFRAME[lines] Start Pos=0 and Pulse Width=1, Color Depth = 4 Bpp, Swivelview = 0 deg, Custom Panel, Panel Invert boxes not checked. CLOCKS TAB CLKI [kHz] grey 50000 auto, CLKI2 [kHz] grey 25000 auto, BCLK Source and Divide CLKI and 1:1, MCLK Source and Divide CLKI and 1:1, PCLK Source and Divide CLKI2 and grey 2:1 and Auto, PWMClk/CVPulse Source = CLKI, PWM no checks and PWM Clk Div = 1 and Duty Cycle = 0, Contrast Voltage no checks and CV Pulse Div= 1 and Burst Len = 1. OTHER TABS WERE NOT SET BY ME AND SEEMED TO DEFAULT CORRECTLY TO MY PC'S PARAMETERS. The SED1376 has only 80KB memory, which prevents it from displaying 8bpp color at 640x240 and which seems to also prevent it from displaying 8bpp color at 320x240. 76B-65.exe configured as above will display 640x240x1 images. Robert Joslyn 3/15/2001 800-826-0527 ================================================ 1376PLAY - test utility - version 1.02 (HAL 1.02) = [0000] 28 14 0B 00 00 13 00 00-00 00 00 00 E0 20 90 00 [0010] D0 00 51 00 4F 00 00 00-FA 00 00 00 EF 00 00 00 [0020] 87 00 00 00 80 00 00 00-1F 00 00 00 00 00 00 00 [0070] 02 00 00 00 00 00 00 00-50 00 00 00 00 00 00 00 [0080] 50 00 00 00 00 00 00 00-00 00 00 00 4F 00 00 00 [0090] EF 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 [00A0] 00 00 00 00 00 00 00 00-00 80 00 00 00 80 00 00 [00B0] 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 GCP Data Registers: [0000] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [0010] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 = =================================================================== //---------------------------------------------------------------------------- // File generated by 1376CFG.EXE // **** FILE 76B-65.csv // **** Formatted print of registers configured in 76B-65.exe above. //---------------------------------------------------------------------------- // Panel: 640x240x4bpp 75Hz Color Single STN 8-bit (PCLK=12.500MHz) (Format 2) 0x0004, 0x00, BUSCLK MEMCLK Config Register ,0x0005, 0x13, PCLK Config Register 0x0010, 0xd0, PANEL Type Register ,0x0011, 0x00, MOD Rate Register 0x0012, 0x51, Horizontal Total Register ,0x0014, 0x4f, Horizontal Display Period Register 0x0016, 0x00, Horizontal Display Period Start Pos Register 0 ,0x0017, 0x00, Horizontal Display Period Start Pos Register 1 0x0018, 0xfa, Vertical Total Register 0 ,0x0019, 0x00, Vertical Total Register 1 0x001c, 0xef, Vertical Display Period Register 0 ,0x001d, 0x00, Vertical Display Period Register 1 0x001e, 0x00, Vertical Display Period Start Pos Register 0 ,0x001f, 0x00, Vertical Display Period Start Pos Register 1 0x0020, 0x87, Horizontal Sync Pulse Width Register ,0x0022, 0x00, Horizontal Sync Pulse Start Pos Register 0 0x0023, 0x00, Horizontal Sync Pulse Start Pos Register 1 ,0x0024, 0x80, Vertical Sync Pulse Width Register 0x0026, 0x00, Vertical Sync Pulse Start Pos Register 0 ,0x0027, 0x00, Vertical Sync Pulse Start Pos Register 1 0x0070, 0x02, Display Mode Register ,0x0071, 0x00, Special Effects Register 0x0074, 0x00, Main Window Display Start Address Register 0 ,0x0075, 0x00, Main Window Display Start Address Register 1 0x0076, 0x00, Main Window Display Start Address Register 2 ,0x0078, 0x50, Main Window Address Offset Register 0 0x0079, 0x00, Main Window Address Offset Register 1 ,0x007c, 0x00, Sub Window Display Start Address Register 0 0x007d, 0x00, Sub Window Display Start Address Register 1 ,0x007e, 0x00, Sub Window Display Start Address Register 2 0x0080, 0x50, Sub Window Address Offset Register 0 ,0x0081, 0x00, Sub Window Address Offset Register 1 0x0084, 0x00, Sub Window X Start Pos Register 0 ,0x0085, 0x00, Sub Window X Start Pos Register 1 0x0088, 0x00, Sub Window Y Start Pos Register 0 ,0x0089, 0x00, Sub Window Y Start Pos Register 1 0x008c, 0x4f, Sub Window X End Pos Register 0 ,0x008d, 0x00, Sub Window X End Pos Register 1 0x0090, 0xef, Sub Window Y End Pos Register 0 ,0x0091, 0x00, Sub Window Y End Pos Register 1 0x00a0, 0x00, Power Save Config Register ,0x00a1, 0x00, CPU Access Control Register 0x00a2, 0x00, Software Reset Register ,0x00a3, 0x00, BIG Endian Support Register 0x00a4, 0x00, Scratch Pad Register 0 ,0x00a5, 0x00, Scratch Pad Register 1 0x00a8, 0x00, GPIO Config Register 0 ,0x00a9, 0x80, GPIO Config Register 1 0x00ac, 0x00, GPIO Status Control Register 0 ,0x00ad, 0x00, GPIO Status Control Register 1 0x00b0, 0x00, PWM CV Clock Control Register ,0x00b1, 0x00, PWM CV Clock Config Register 0x00b2, 0x00, CV Clock Burst Length Register ,0x00b3, 0x00, PWM Clock Duty Cycle Register