**** AGGREGATE FILE 76-T57.txt 8/13/03 **** ============================================================================== **** FILE 76B-T57.txt **** The Epson S1D13706 register settings below were produced by the Epson configuration program 13706CFG.exe as it was configuring a copy of the Epson program 13706BMP.exe to display 320x240x8 images on a prototype TCG057QV1AA-G00 Kyocera TFT LCD module. The S1D13706 controller IC was on an SDU1376BOC evaluation board by Epson. CONNECTIONS This board was mounted in a PCI slot and connected to a special Kyocera interface board via a 40pin cable. The special interface board was connected to the Kyocera TFT LCD via its attached 33 pin, 0.5mm pitch white FFC cable. An ideal connection list follows this text. The actual cable used for testing was wired for the S1D13506 so some color fidelity must have been lost, although it was not noticed at the time. CONFIGURATION A copy of 13706BMP.EXE, renamed 76B-T57.EXE, was opened, configured as described below, then saved. The TABs refer to the configuration screens in the configuration program 13706CFG.exe. REQUIRED CONFIGURATION SETTINGS (The following settings are absolutely required by the TCG057QV LCD) PANEL TAB TFT; 18 bit; Single; Color; FPline Lo; FPframe Lo; 320 width; 240 height. ADJUSTABLE CONFIGURATION SETTINGS (The following settings are interelated and many different combinations are possible. Anytime you change a value, 13706CFG.exe may change some other value to make your change possible. Play with it until all values are satisfactory. Here is what was used for the first trial.) PANEL TAB Display total horz 392 pixels and vert 263 lines; Display start horz 67 pixels and vert 22 lines; Timings Frame rate 76 Hz and Pixel clock 7.875 MHz; TFT/FPLINE [pixels] Start pos 48 and Pulse width 16; TFT/FPFRAME [lines] Start pos 15 and Pulse width 2. CLOCKS TAB (Nothing was set under this tab. The values shown are the result of settings made under the PANEL TAB.) CLKI Timing is Auto and 50.000 MHz is shown; CLKI2 timing is Auto and 31.500 MHz is shown; PCLK Source is CLKI2, Divide is auto and 7.875 MHz is shown; BCLK Source is CLKI, divide is 1:1 and 50.000 MHz is shown; MCLK Source is BCLK, Divide is 1:1 and 50.000 MHz is shown; PWMCLK Enable box is unchecked, Force High box is unchecked, Source is CLKI, Divide is 1:1, Timing shows 50.000MHz, Duty cycle 0; Contrast Voltage Pulse Enable box is unchecked, Force High box is unchecked, Source is CLKI, Divide is 1:1, Timing shows 50.000MHz, Burst Length 1. PREFERENCE TAB Panel Swivel View is 0 deg; Panel color depth is 8 bpp; Panel invert boxes are both unchecked. Panel Power TAB (all defaults) Time delay between bias power-off and control signals inactive is 1200 ms; Time delay between control signals active and and bias power-on is 50 ms. GENERAL TAB (all defaults) Decode addresses for Epson S5U13706B00B/B00C. Run 13706CFG.exe under Windows and open 13706BMP.exe or a copy of it, to get the initial values. Then modify the values as above and save. Run the copy renamed 76B-T57.exe and configured as above at the prompt on the MS-DOS EMULATION WINDOW. For example c:\...>76B-T57 xxxxxx.bmp This would display the bitmap file xxxxxx.bmp on the LCD. Display memory is integrated onto the S1D13706 IC, but only 80 KB. So at the LCD's full 320x240 size, images are limited to 8 bits of color. ============================================================================== IDEAL CONNECTION LIST FOR TFT DEMONSTRATION INTERFACE BOARD (This cable should be different from the S1D13506 cable because it should provide full 18 bit color and fewer GNDs. Epson Eval Kyocera TFT Board 40pin 33pin FFC name pin pin name note FPDAT0 1 11 R5 FPDAT1 3 10 R4 FPDAT2 5 9 R3 FPDAT3 7 18 G5 FPDAT4 9 17 G4 FPDAT5 11 16 G3 FPDAT6 13 25 B5 FPDAT7 15 24 B4 FPDAT8 17 23 B3 FPDAT9 19 8 R2 FPDAT10 21 7 R1 FPDAT11 23 6 R0 FPDAT12 25 15 G2 FPDAT13 27 14 G1 FPDAT14 29 13 G0 FPDAT15 31 22 B2 FPDAT16 4 21 B1 FPDAT17 6 20 B0 FPSHIFT 33 2 CK DRDY 35 27 ENAB FPLINE 37 3 HSYNC FPFRAME 39 4 VSYNC GPO 40 n/c DRDY 38 n/c VDDH 36 n/c +12V 34 n/c VCC 32-+-28 VDD +-29 VDD +-31 U/D U/D tied high for normal operation. VLCD 30 n/c PWMOUT 28 n/c GND 26 1 GND GND 20 5 GND GND 14-+-12 GND +-19 GND GND 8-+-26 GND +-30 R/L R/L tied to GND for normal operation. +-32 V/Q V/Q tied to GND for normal operation. GND 2-+-33 GND ============================================================================== Below are the register contents resulting from the above configuration, obtained by the export command for generic in 13706CFG.exe, exported as a file named S1D13706.h Robert Joslyn 8/13/2003 800-826-0527 //---------------------------------------------------------------------------- // // File generated by S1D13706CFG.EXE // // Copyright (c) 2000,2001 Epson Research and Development, Inc. // All rights reserved. // //---------------------------------------------------------------------------- // Panel: 320x240x8bpp 76Hz Color TFT 18-bit (PCLK=7.875MHz) #define S1D_DISPLAY_WIDTH 320 #define S1D_DISPLAY_HEIGHT 240 #define S1D_DISPLAY_BPP 8 #define S1D_DISPLAY_SCANLINE_BYTES 320 #define S1D_PHYSICAL_VMEM_ADDR 0x00000000L #define S1D_PHYSICAL_VMEM_SIZE 0x14000L #define S1D_PHYSICAL_REG_ADDR 0x00000000L #define S1D_PHYSICAL_REG_SIZE 0x100 #define S1D_DISPLAY_PCLK 7875 #define S1D_PALETTE_SIZE 256 #define S1D_REGDELAYOFF 0xFFFE #define S1D_REGDELAYON 0xFFFF #define S1D_WRITE_PALETTE(p,i,r,g,b) \ { \ ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ } #define S1D_READ_PALETTE(p,i,r,g,b) \ { \ ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ } typedef unsigned short S1D_INDEX; typedef unsigned char S1D_VALUE; typedef struct { S1D_INDEX Index; S1D_VALUE Value; } S1D_REGS; static S1D_REGS aS1DRegs[] = { {0x04,0x00}, // BUSCLK MEMCLK Config Register {0x05,0x33}, // PCLK Config Register {0x10,0x61}, // PANEL Type Register {0x11,0x00}, // MOD Rate Register {0x12,0x30}, // Horizontal Total Register {0x14,0x27}, // Horizontal Display Period Register {0x16,0x3E}, // Horizontal Display Period Start Pos Register 0 {0x17,0x00}, // Horizontal Display Period Start Pos Register 1 {0x18,0x06}, // Vertical Total Register 0 {0x19,0x01}, // Vertical Total Register 1 {0x1C,0xEF}, // Vertical Display Period Register 0 {0x1D,0x00}, // Vertical Display Period Register 1 {0x1E,0x16}, // Vertical Display Period Start Pos Register 0 {0x1F,0x00}, // Vertical Display Period Start Pos Register 1 {0x20,0x0F}, // Horizontal Sync Pulse Width Register {0x22,0x2F}, // Horizontal Sync Pulse Start Pos Register 0 {0x23,0x00}, // Horizontal Sync Pulse Start Pos Register 1 {0x24,0x01}, // Vertical Sync Pulse Width Register {0x26,0x0F}, // Vertical Sync Pulse Start Pos Register 0 {0x27,0x00}, // Vertical Sync Pulse Start Pos Register 1 {0x70,0x03}, // Display Mode Register {0x71,0x00}, // Special Effects Register {0x74,0x00}, // Main Window Display Start Address Register 0 {0x75,0x00}, // Main Window Display Start Address Register 1 {0x76,0x00}, // Main Window Display Start Address Register 2 {0x78,0x50}, // Main Window Address Offset Register 0 {0x79,0x00}, // Main Window Address Offset Register 1 {0x7C,0x00}, // Sub Window Display Start Address Register 0 {0x7D,0x00}, // Sub Window Display Start Address Register 1 {0x7E,0x00}, // Sub Window Display Start Address Register 2 {0x80,0x50}, // Sub Window Address Offset Register 0 {0x81,0x00}, // Sub Window Address Offset Register 1 {0x84,0x00}, // Sub Window X Start Pos Register 0 {0x85,0x00}, // Sub Window X Start Pos Register 1 {0x88,0x00}, // Sub Window Y Start Pos Register 0 {0x89,0x00}, // Sub Window Y Start Pos Register 1 {0x8C,0x4F}, // Sub Window X End Pos Register 0 {0x8D,0x00}, // Sub Window X End Pos Register 1 {0x90,0xEF}, // Sub Window Y End Pos Register 0 {0x91,0x00}, // Sub Window Y End Pos Register 1 {0xA0,0x00}, // Power Save Config Register {0xA1,0x00}, // CPU Access Control Register {0xA2,0x00}, // Software Reset Register {0xA3,0x00}, // BIG Endian Support Register {0xA4,0x00}, // Scratch Pad Register 0 {0xA5,0x00}, // Scratch Pad Register 1 {0xA8,0x00}, // GPIO Config Register 0 {0xA9,0x80}, // GPIO Config Register 1 {0xAC,0x00}, // GPIO Status Control Register 0 {0xAD,0x00}, // GPIO Status Control Register 1 {0xB0,0x00}, // PWM CV Clock Control Register {0xB1,0x00}, // PWM CV Clock Config Register {0xB2,0x00}, // CV Clock Burst Length Register {0xB3,0x00}, // PWM Clock Duty Cycle Register }; //----------------------------------------------------------------------------