**** AGGREGATE FILE 76-G47.txt 10/31/03 **** ==================================================== **** FILE 76B-G47.txt **** This document shows how to use the Epson program 13706CFG.exe to determine the Epson S1D13706 controller IC register settings for the Kyocera KCG047QV.. LCD and how to put the register settings into an executable file and test them on the LCD. The S1D13706 was on an SDU1376BOC evaluation board by Epson. BEGIN with a MS-Windows computer with an open PCI slot. Copy the "drivers" from the S1D13xxx folder into the root directory. Copy the Epson S1D13706 software utilities into a working folder. Copy 13706BMP.EXE into the same folder to create a duplicate. Rename the duplicate 76B-G47.EXE Power down for connections. CONNECTIONS This board was mounted in a PCI slot and connected to a Kyocera KK-5 No.1 interface board via a 40pin cable. The KK-5 was connected to a Kyocera KK-7 connector board LCD via a red Molex cable, which was inserted in the KK-5 connector with white paper label saying "CN6" and into the KK-7 connector named CN5 by screen printing on the board. The KCG LCD was connected to the KK-7 board by a white 20-pin FFC. RUN 13706CFG.EXE under windows File->Open->56B-G57.EXE GENERAL TAB Select Epson S5u13706... PREFERENCE TAB Initial Display: select Panel Panel Swivel View: select 0 degrees Pixel Color Depth: select 8 bpp MEMORY TAB: accept all defaults PANEL TAB: (The following settings are absolutely required by the Kyocera KCG047QV LCD panel) Panel Settings: select STN, select 8 bit Panel Color: select Color, select Format 2 Polarity: select FPLINE Hi and FPFRAME Hi Panel Dimensions: Width select 320, Height select 240 (The following settings are interelated and many different combinations are possible.) Display total: H[pixels] 352, V[lines] 251 Display start: h[pixels] 22, V[lines] 0 Timings: Pixel Clock select 6.666 mHz which sets frame rate to 75 Hz. (Section 5 of the Kyocera spec gives the required range of the shift clock frequency. The maximum shift clock frequency is important. The maximum frame rate frequency does not matter. Shift-clock-Freq = (3/8) x Pixel-Clock-Freq 3 comes from 3 LCD subpixels per pixel. 8 comes from 8 data lines per clock pulse. TFT/FPLINE [pixels]: Start pos 1, Pulse width 8 TFT/FPFRAME [lines]: Start pos 1, Pulse width 1 Predefined panels: Custom Panel CLOCKS TAB (Do not set anything under this tab because the values are set by your selection of pixel clock frequency and Display total. If you do set frequencies in the CLOCKS TAB, then please go back to the PANEL TAB and note the changes which were automatically made.) REGISTERS TAB File->Export->Generic change name from S1D13506.H to 76B-G47.H Click Export (eventually give this .h file to your software engineers) File->Save (which patches the above register settings into the executable code in 76B-G47.EXE) TEST THE SETTINGS Start the MS-DOS emulation window (not RUN ..) >CD {your working folder} >76B-G47 {observe the Help info} >76B-G47 PE8-3224.BMP {or other sample bitmap} Of course you will need an inverter to power the LCD backlight and a cable and a 12V power supply to power the inverter. This program seems to display any .bmp image on the Kyocera KCG047QV. It displays the image in the upper left corner and black fills any non-image area to the right and truncates images longer than 240 lines, just as you would expect. The S1D13706 has only 80KB of memory, and it seems to be able to display images up to this size. The default color depth of 8 bpp under the PREFERENCE TAB seems to an initializing value, used by the program before it opens the .bmp file. Below are the register values as formatted above in 76B-G47.H Robert Joslyn 10/31/03 800-826-0527 or 360-750-6121 //---------------------------------------------------------------------------- // // File generated by S1D13706CFG.EXE // // Copyright (c) 2000,2001 Epson Research and Development, Inc. // All rights reserved. // //---------------------------------------------------------------------------- // Panel: 320x240x8bpp 75Hz Color Single STN 8-bit (PCLK=6.666MHz) (Format 2) #define S1D_DISPLAY_WIDTH 320 #define S1D_DISPLAY_HEIGHT 240 #define S1D_DISPLAY_BPP 8 #define S1D_DISPLAY_SCANLINE_BYTES 320 #define S1D_PHYSICAL_VMEM_ADDR 0x00000000L #define S1D_PHYSICAL_VMEM_SIZE 0x14000L #define S1D_PHYSICAL_REG_ADDR 0x00000000L #define S1D_PHYSICAL_REG_SIZE 0x100 #define S1D_DISPLAY_PCLK 6666 #define S1D_PALETTE_SIZE 256 #define S1D_REGDELAYOFF 0xFFFE #define S1D_REGDELAYON 0xFFFF #define S1D_WRITE_PALETTE(p,i,r,g,b) \ { \ ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ } #define S1D_READ_PALETTE(p,i,r,g,b) \ { \ ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ } typedef unsigned short S1D_INDEX; typedef unsigned char S1D_VALUE; typedef struct { S1D_INDEX Index; S1D_VALUE Value; } S1D_REGS; static S1D_REGS aS1DRegs[] = { {0x04,0x00}, // BUSCLK MEMCLK Config Register {0x05,0x23}, // PCLK Config Register {0x10,0xD0}, // PANEL Type Register {0x11,0x00}, // MOD Rate Register {0x12,0x2B}, // Horizontal Total Register {0x14,0x27}, // Horizontal Display Period Register {0x16,0x00}, // Horizontal Display Period Start Pos Register 0 {0x17,0x00}, // Horizontal Display Period Start Pos Register 1 {0x18,0xFA}, // Vertical Total Register 0 {0x19,0x00}, // Vertical Total Register 1 {0x1C,0xEF}, // Vertical Display Period Register 0 {0x1D,0x00}, // Vertical Display Period Register 1 {0x1E,0x00}, // Vertical Display Period Start Pos Register 0 {0x1F,0x00}, // Vertical Display Period Start Pos Register 1 {0x20,0x87}, // Horizontal Sync Pulse Width Register {0x22,0x00}, // Horizontal Sync Pulse Start Pos Register 0 {0x23,0x00}, // Horizontal Sync Pulse Start Pos Register 1 {0x24,0x80}, // Vertical Sync Pulse Width Register {0x26,0x01}, // Vertical Sync Pulse Start Pos Register 0 {0x27,0x00}, // Vertical Sync Pulse Start Pos Register 1 {0x70,0x03}, // Display Mode Register {0x71,0x00}, // Special Effects Register {0x74,0x00}, // Main Window Display Start Address Register 0 {0x75,0x00}, // Main Window Display Start Address Register 1 {0x76,0x00}, // Main Window Display Start Address Register 2 {0x78,0x50}, // Main Window Address Offset Register 0 {0x79,0x00}, // Main Window Address Offset Register 1 {0x7C,0x00}, // Sub Window Display Start Address Register 0 {0x7D,0x00}, // Sub Window Display Start Address Register 1 {0x7E,0x00}, // Sub Window Display Start Address Register 2 {0x80,0x50}, // Sub Window Address Offset Register 0 {0x81,0x00}, // Sub Window Address Offset Register 1 {0x84,0x00}, // Sub Window X Start Pos Register 0 {0x85,0x00}, // Sub Window X Start Pos Register 1 {0x88,0x00}, // Sub Window Y Start Pos Register 0 {0x89,0x00}, // Sub Window Y Start Pos Register 1 {0x8C,0x4F}, // Sub Window X End Pos Register 0 {0x8D,0x00}, // Sub Window X End Pos Register 1 {0x90,0xEF}, // Sub Window Y End Pos Register 0 {0x91,0x00}, // Sub Window Y End Pos Register 1 {0xA0,0x00}, // Power Save Config Register {0xA1,0x00}, // CPU Access Control Register {0xA2,0x00}, // Software Reset Register {0xA3,0x00}, // BIG Endian Support Register {0xA4,0x00}, // Scratch Pad Register 0 {0xA5,0x00}, // Scratch Pad Register 1 {0xA8,0x00}, // GPIO Config Register 0 {0xA9,0x80}, // GPIO Config Register 1 {0xAC,0x00}, // GPIO Status Control Register 0 {0xAD,0x00}, // GPIO Status Control Register 1 {0xB0,0x00}, // PWM CV Clock Control Register {0xB1,0x00}, // PWM CV Clock Config Register {0xB2,0x00}, // CV Clock Burst Length Register {0xB3,0x00}, // PWM Clock Duty Cycle Register };