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STN Signal Interface
This page describes how to display pixels of light on the LCD screen.
Every Kyocera STN color LCD has interface signals named LOAD, FRM, CP and DISP as well as 8 or 16 data lines. Using these signals, a controller IC or other device can make colored pixels appear on the screen of the LCD. The Kyocera 5.7 inch
STN LCD is the simplest example and a simplified block diagram of one is shown below.
A pixel is a square dot of color, but it really consists of narrow red, blue and green subpixels, side-by-side. In this example, the format of the screen would be described as 320 x 240 pixels, meaning 320 pixels across and 240 rows, and system software and controller ICs would be configured for 320 x 240. But at the interface level, each row requires 960 bits, one for each subpixel and controller ICs provide these 960 bits when configured for 320 pixels.
Data is sent to the LCD one row at a time, followed by a pulse on the LOAD signal, which causes the data to be latched into place and displayed on the next row. When the FRM signal is asserted high, LOAD causes the data to be displayed on the first (top) row. The latch action takes place when LOAD falls from high to low.
Smaller Kyocera displays like this example have 8 data lines named D0, D1, ... D6, D7. Data is placed on these lines and clocked in by a falling pulse on the CP line. For 320 pixels, there will be 320 x 3 = 960 bits per row. With 8 data lines there will be 960/8 = 120 clock pulses on CP per row. Bits are placed on the data lines as shown below, where R, G, B are abbreviations for Red, Green, Blue followed by the pixel number.
| CP Pulse => |
1 |
2 |
----- |
120 |
| Signal |
|
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|
| D7 |
R1 |
B3 |
----- |
G318 |
| D6 |
G1 |
R4 |
----- |
B318 |
| D5 |
B1 |
G4 |
----- |
R319 |
| D4 |
R2 |
B4 |
----- |
G319 |
| D3 |
G2 |
R5 |
----- |
B319 |
| D2 |
B2 |
G5 |
----- |
R320 |
| D1 |
R3 |
B5 |
----- |
G320 |
| D0 |
G3 |
R6 |
----- |
B320 |
The 320x240 format in this example is called single scan QVGA. Larger displays
often use a 640x480 format called VGA or a 800x600 format called SVGA. Most legacy STN
600 row and 480 row displays are dual scan. This means that the top and bottom
halves of the screen would have separate data lines. The D0..D7 signals shown above
would be renamed HD0..HD7. There would also be driver ICs along the bottom edge of
the screen and their separate data lines would be named LD0..LD7. There would still
be a single signal CP which would clock in both sets of data signals. The advantage
of dual scan VGA is that the duty cycle is still a fundamentally bright 1 of 240
lines displayed simultaneously on each half. The improved brightness of the V-series
STN LCDs has allowed Kyocera to introduce single scan 640x480 STN LCDs, like the
KCG075VG2BE-G00, even though the duty cycle is 1 of 482.
Notice that the data and CP signals are connected only to the column driver ICs,
not the row drivers. LOAD is connected to column driver ICs to latch the data and
is connected to the row driver ICs to increment the current row. The FRM signal is
connected only to the row driver ICs to reset the current row. The DISP signal
is connected to both the row and driver ICs and must be held high during normal
operation. It should be held low to suppress display artifacts during power-up
and power-down.
Kyocera TFT LCDs have a different technology. Each TFT pixel consists of 18 bits
which are all clocked in together. There are still three subpixels per pixel.
The brightness of each subpixel is defined by 6 bits which determine the charge
level of an on-screen capacitor. Each capacitor preserves the voltage across the subpixel cell long after the scan line has moved on. So there is no penalty for
a 1 of 480 duty cycle. For this reason, if power is
abruptly removed from the interface, the image on a TFT LCD
lingers a few seconds compared to STN LCDs.
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