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Logic Voltage
The driver ICs and other circuits on Kyocera LCDs require a logic
voltage. Newer LCDs are specified for 3.3V ± 0.3V. Some older
STN LCDs are specified for 5.0V ± 5%. Any Kyocera
STN LCD specified for 3.3V logic will run OK at 5.0V.
The reverse is not necessarily true. If you want to use an 5.0V
STN LCD at 3.3V logic voltage, please check with Kyocera. It may be
permissible. It is not permissible with the KCS057 and KHS057 lines
of 5.7 inch LCDs, which must run at the specified 5.0V.
The above is not true of TFT LCDs. A 3.3V TFT LCD will not run
at 5.0V unless the spec explicitly allows 5.0V. The TCG057, TCG062
and TCG075 do not specify 5.0V. The TCG104 does allow 5.0V
The STN LCDs KHS072VG1AB-G00
and KCG057QV1DB-G50
are actually specified for both voltages. Close examination of sections 5
and 11 of these specs shows the effect of changing the logic voltage.
At 5.0 volts, switching speed is faster, which allows a higher maximum
data clock speed. A higher clock speed enables a faster frame rate,
which means better quality of intermediate colors, although power
consumption increases slightly.
3.3 vs 5.0 Volt Logic on KHS072VG1AB-G00
| Section 5. Electrical Characteristics |
VDD = 3.3 V |
VDD = 5.0 V |
| Item |
Min |
Typ |
Max |
Min |
Typ |
Max |
| Logic voltage VDD |
3.0 |
3.3 |
3.6 |
4.75 |
5.00 |
5.25 |
LCD driving voltage
VCONT at 0°C
VCONT at 25°C
VCONT at 50°C |
0.80
1.35
- |
-
1.95
- |
-
2.55
2.80 |
0.80
1.35
- |
-
1.95
- |
-
2.55
2.80 |
| Clock frequency (MHz) |
4.03 |
4.32 |
10.0 |
4.02 |
4.32 |
16.0 |
| Frame frequency (Hz) |
70 |
75 |
- |
70 |
75 |
- |
| Logic current (mA) |
- |
120 |
180 |
- |
86 |
129 |
| Power consumption (mW) |
- |
396 |
594 |
- |
430 |
645 |
| Section 11. Switching Characteristics (units ns) |
VDD = 3.3 V |
VDD = 5.0 V |
| Item |
Symbol |
Min |
Max |
Min |
Max |
| CP cycle |
tCCL |
100 |
- |
62 |
- |
| CP "H" pulse width |
tWCLH |
40 |
- |
25 |
- |
| CP "L" pulse width |
tWCLL |
40 |
- |
25 |
- |
| CP rise time |
trCP |
- |
30 |
- |
30 |
| CP fall time |
tfCP |
- |
30 |
- |
30 |
| Data setup time |
tDS |
30 |
- |
25 |
- |
| Data hold time |
tDH |
20 |
- |
20 |
- |
| LOAD "H" pulse width |
tWLPH |
100 |
- |
50 |
- |
| LOAD "L" pulse width |
tWLPL |
4900 |
- |
370 |
- |
| LOAD cycle |
tLCL |
5000 |
- |
420 |
- |
| CP→LOAD delay time |
tCL |
0 |
- |
0 |
- |
| LOAD→CP delay time |
tLC |
200-tWLPH |
- |
120-tWLHP |
- |
| Input signal rise time |
tr |
- |
30 |
- |
30 |
| Input signal fall time |
tf |
- |
30 |
- |
30 |
| FRM data setup time |
tFS |
100 |
- |
100 |
- |
| FRM data hold time |
tFH |
30 |
- |
30 |
- |
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